1. Field of the Invention
This invention relates generally to non-volatile memories, and, more specifically, to methods of reducing disturbs in electrically erasable and programmable read only memories (EEPROMs).
2. Background Information
A non-volatile memory cell stores information by altering the control gate voltage required to enable source-drain current conduction. This is known as the cell""s threshold voltage, Vt. Programming is the operation used to change this conduction threshold in order to store information on the cell. The memory cells are conventionally arranged in an array, with rows defined by word lines, columns defined by bit lines, and the cells identified by the word lines and bit lines to which they are attached.
A portion of such an array of memory cells is shown schematically in FIG. 1. In this figure, the word lines 120 and bit lines 110 form a grid. The detail shows an example of how a cell may be place within this array. In this particular example, the cell is taken to consist of a pair of transistors, the select transistor 142 and the floating gate transistor 141 on which the information is stored through alteration of its threshold voltage, which both have their control gates connected to the word line 121. This example also shows a virtual-ground architecture where the adjoining cells sharing bit lines, with the cell composed of transistors 141 and 142 connected between bit lines 111 and 112. A number of other cells, structures, and architectures can be used for the array. These are discussed more fully in U.S. Pat. Nos. 5,172,338 and 5,095,344, both of which are assigned to SanDisk Corporation, and both of which are hereby incorporated herein by this reference.
As with most devices, EEPROMs and Flash EEPROMs are susceptible to defects and failures. One way errors can occur is by the shifting of the threshold level of the memory states. This shifting is partly due to ambient conditions, but more often due to stress from normal operations of the memory device, such as erase, program or read. These errors, and methods for dealing with them, are discussed in more fully in U.S. Pat. Nos. 5,418,752 and 5,532,962, both of which are assigned to SanDisk Corporation and both of which are hereby incorporated herein by this reference, and also in U.S. Pat. Nos. 5,172,338 and 5,095,344, which were incorporated by reference above.
One mechanism that affects the threshold values of the memory cells is a xe2x80x9cprogram disturbxe2x80x9d. When the memory array is a two dimensional matrix as in FIG. 1, each bit line, such as 111, of the set of bit lines 110 runs through all of the word lines 120. To program a cell, a voltage is applied across the cell""s drain and source through the bit lines. At the same time, the cell must be also be activated by a voltage to its control gate. For example, the column containing the cell is enable by having its source bit line raised to a high voltage of, say, 6-8 volts relative to its drain bit line. The cell to be programmed is then addressed by applying pulses of, say, 10-12 volts to its word line. Other cells within the same column are not addressed since their word lines are non-selected and placed at zero potential; nevertheless, they may be affected by the program operation of the addressed cell because of the high voltage on the common bit line and the other bit lines as well. This may induce electric charge leakage in these non-addressed cells, resulting in either a gain or loss of electric charge in their floating gate depending on the electrical mechanism.
The patents above include a number of techniques for treating such errors, such as the use of error correcting code (ECC) and a refresh, or xe2x80x9cscrubbingxe2x80x9d, operation. However, the number or severity of the errors can become sufficient to overwhelm these methods and result in a degradation of the data stored in the memory. Therefore, it is preferable to reduce both the number and severity of such disturbs.
It has been found that a source of disturbs is the displacement current generated in non-selected word lines of an array that results when the voltage levels on array""s bit lines are changed. Due to the capacitive coupling between the word lines and the bit lines, each of the bit lines crossing a word line contributes an amount proportional to the rate at which the voltage level on the bit line is changed. Because of the non-perfect conductivity of the word lines, this induced current results in a voltage developed on the control gates of memory cells along the non-selected word lines and, consequently, may result in disturbs.
In a first aspect of the present invention, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This can be done by selecting the number and order of units to be programmed in parallel such that only units from distinct planes are programmed together. Alternately, or additionally, the units to be programmed can be compared to see if any are from the same plane and writing those units that are in the same plane sequentially.
In a second, complementary aspect of the present invention, the rate at which the voltage levels in the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device""s application, the rate at which the bit line drivers change the bit line voltage is adjusted. This can be implemented by setting the rate externally, or by the controller, based upon device performance and the amount of data error being generated.
Additional aspects, features and advantages of the present invention are included in the following description of specific representative embodiments, which description should be taken in conjunction with the accompanying drawings.